# Book Chapters

**H. Jiao**and V. Kursun, “Tri-Mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits,”*VLSI-SoC: Forward-Looking Trends in IC and System Design*, J. L. Ayala, D. A. Atienza, and R. Reis, (Eds.), Springer, pp. 258 – 290, 2012, ISBN 978-3-642-28565-3.

# Journal Papers

* Corresponding author # Authors with equal contribution ^ Supervised student as first author

- S. Qiu^, W. Wang, and
**H. Jiao***, “LightSeizureNet: A Lightweight Deep Learning Model for Real-Time Epileptic Seizure Detection,”, 2022.*IEEE Journal of Biomedical and Health Informatics* - J. Sun^, H. Guo#, G. Li#, and
**H. Jiao***, “An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit,”, Vol. 57, No. 11, pp. 3477-3489, November 2022.*IEEE Journal of Solid-State Circuits* - P. Detterer^*, M. Nabi,
**H. Jiao**, and T. Basten, “Receiver Design with An Adjustable Energy-Signal-Quality Trade-off for IoT Networks,”, Vol. 9, No. 22, pp. 23086-23096, November 2022.*IEEE Internet of Things Journal* - Q. Huang#, J. Wang#, C. Lin, J. Zhu, W. Wang, Y. Huang, Y. Zhang,
**H. Jiao**, S. Zhang, H. Meng, M. Zhang*, and X. Wang*, “Intrinsically Flexible All-Carbon-Nanotube Electronics Enabled by A Hybrid Organic-Inorganic Gate Dielectric,”, 2022.*NPJ Flexible Electronics* - Y. Chen^#, Y. Nie^#, and
**H. Jiao***, “An Ultra-Low Power 65-nm Standard Cell Library for Near/Sub-threshold Digital Circuits,”, Vol. 30, No. 5, pp. 676-680, May 2022.*IEEE Transactions on Very Large Scale Integration (VLSI) Systems* - X. Cao^,
**H. Jiao***, and E. J. Marinissen, “A Bypassable Scan Flip-flop for Low Power Testing with Data Retention Capability,”, Vol. 69, No. 2, pp. 554-558, February 2022.*IEEE Transactions on Circuits and Systems II* - H.-M. Lam, S. Lu, H. Qiu, M. Zhang,
**H. Jiao***, and S. Zhang*, “A High-Efficiency Segmented Reconfigurable Cyclic Shifter for 5G QC-LDPC Decoder,”, Vol. 69, No. 1, pp. 401-414, January 2022.*IEEE Transactions on Circuits and Systems I* - Y. Huang, Y. Chen*,
**H. Jiao**, P.-I. Mak, and R. P. Martins, “A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques,”, Vol. 68, No. 9, pp. 3093-3097, September 2021.*IEEE Transactions on Circuits and Systems II* - S. Shen, C. Liao*, J. Yang,
**H. Jiao**, and S. Zhang*, “A Compact Gate Driver with Bifunctional Capacitor for In-Cell Touch Mobile Display,”, Vol. 29, No. 7, pp. 526-536, July 2021.*Wiley Journal of Society for Information Display* - K. Singh^*, B. de Bruin,
**H. Jiao**, J. Huisken, H. Corporaal, and J. Pineda de Gyvez, “Converter-Free Power Delivery Using Voltage Stacking for Near/sub-threshold Operation,”, Vol. 29, No. 6, pp. 1039-1051, June 2021.*IEEE Transactions on Very Large Scale Integration (VLSI) Systems* - H.-M. Lam, F. Guo, H. Qiu, M. Zhang,
**H. Jiao***, and S. Zhang*, “Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers,”, Vol. 31, No. 5, pp. 2056-2062, May 2021.*IEEE Transactions on Circuits and Systems for Video Technology* - P. Detterer^*, M. Nabi,
**H. Jiao**, and T. Basten, “Receiver-Sensitivity Control for Energy-Efficient IoT Networks,”, Vol. 25, No. 4, pp. 1383-1386, April 2021.*IEEE Communications Letters* - S. Shen, C. Liao*, J. Yang,
**H. Jiao**, and S. Zhang*, “Capacitor Reused Gate Driver for Compact In-cell Touch Displays,”, Vol. 9, pp. 533-538, 2021.*IEEE Journal of the Electron Devices Society* - H.-M. Lam, H. Qiu, C. Li, J. Wen, W. Bai, C. Liao, M. Zhang,
**H. Jiao***, and S. Zhang*, “Fast Progressive Compensation Method for Externally Compensated AMOLED Displays,”, Vol. 9, pp. 257-264, 2021.*IEEE Journal of the Electron Devices Society* - Y. Sun, W. He*, Z. Mao,
**H. Jiao**, and V. Kursun, “Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density,”, Vol. 67, No. 7, pp. 2431-2441, July 2020.*IEEE Transactions on Circuits and Systems I* - J. Liang, S. Yi, W. Bai, L. Wang, C. Zhan, C. Liao, H.-M. Lam, M. Zhang, S. Zhang,
**H. Jiao***, “A 80 dB PSRR 4.99 ppm/°C TC Bandgap Reference with Nonlinear Compensation,”, Vol. 95, 2020.*Elsevier Microelectronics Journal* - X. Huo^, C. Liao, M. Zhang,
**H. Jiao***, and S. Zhang, “A Pixel Circuit With Wide Data Voltage Range for OLEDoS Microdisplays With High Uniformity,”, Vol. 66, No. 11, pp. 4798-4804, November 2019.*IEEE Transactions on Electron Devices* - H.-M. Lam, Y. Wang, M. Zhang,
**H. Jiao***, and S. Zhang, “A Compact Pixel Circuit for Externally Compensated AMOLED Displays,”, Vol. 6, pp. 936-941, 2018.*IEEE Journal of the Electron Devices Society* - Y. Sun*, W. He, Z. Mao,
**H. Jiao**, and V. Kursun, “Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded Memory,”, Vol. 65, No. 3, pp. 1230-1238, March 2018.*IEEE Transactions on Electron Devices* **H. Jiao***, R. Wang, and Y. He, “Crosstalk-Noise-Aware Bus Coding with Low-Power Ground-Gated Repeaters,”, Vol. 46, No. 2, pp. 280-289, February 2018.*Wiley International Journal of Circuit Theory and Applications*- Y. Sun, W. He, Z. Mao,
**H. Jiao***, and V. Kursun, “High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes,”, Vol. 17, No. 1, pp. 20-31, March 2017.*IEEE Transactions on D**evice and Materials Reliability* **H. Jiao***, Y. Qiu, and V. Kursun, “Variability-Aware 7T SRAM Circuit with Low Leakage High Data Stability SLEEP Mode,”, Vol. 53, pp. 68-79, March 2016.*Elsevier Integration, the VLSI Journal***H. Jiao***, Y. Qiu, and V. Kursun, “Low Power and Robust Memory Circuits with Asymmetrical Ground Gating,”, Vol. 48, pp. 109-119, February 2016.*Elsevier Microelectronics Journal*- S. M. Salahuddin*,
**H. Jiao**, and V. Kursun, “FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability,”, Vol. 16, No. 6, pp. 293-302, December 2015.*Transactions on Electrical and Electronic Materials* - Y. Sun*,
**H. Jiao**, and V. Kursun, “A Novel Robust and Low-Leakage SRAM Cell with Nine Carbon Nanotube Transistors,”, Vol. 23, No. 9, pp. 1729-1739, September 2015.*IEEE Transactions on Very Large Scale Integration (VLSI) Systems* **H. Jiao***and V. Kursun, “Mode Transition Timing and Energy Overhead Analysis in Noise-Aware MTCMOS Circuits,”, Vol. 45, No. 8, pp. 1125-1131, August 2014.*Elsevier Microelectronics Journal***H. Jiao***and V. Kursun, “Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits,”, Vol. 21, No. 3, pp. 533-545, March 2013.*IEEE Transactions on Very Large Scale Integration (VLSI) Systems***H. Jiao***and V. Kursun, “Threshold Voltage Tuning for Faster Activation with Lower Noise in Tri-Mode MTCMOS Circuits,”, Vol. 20, No. 4, pp. 741-745, April 2012.*IEEE Transactions on Very Large Scale Integration (VLSI) Systems***H. Jiao***and V. Kursun, “Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits,”, Vol. 19, No. 5, pp. 763-773, May 2011.*IEEE Transactions on Very Large Scale Integration (VLSI) Systems***H. Jiao***and V. Kursun, “Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias,”*World Scientific Journal of Circuits, Systems, and Computers***(Special Issue on Green Integrated Circuits and Systems, Invited Paper)**, Vol. 20, No. 1, pp. 125-145, February 2011.**H. Jiao***and V. Kursun, “Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits,”, Vol. 57, No. 8, pp. 2053-2065, August 2010.*IEEE Transactions on Circuits and Systems I***H. Jiao***and V. Kursun, “Low-Leakage and Compact Registers with Easy-Sleep Mode,”, Vol. 6, No. 2, pp. 263-279, August 2010.*ASP Journal of Low Power Electronics***H. Jiao***, L. Chen, Z. Li, Q. Yang, and T. Ye, “OPC Reuse Based on A Reduced Standard Cell Library,”*IOPscience*Vol. 29, No. 5, pp. 1016-1021, May 2008.**Journal of Semiconductors**,

# Conference Papers

* Corresponding author ^ Supervised student as first author

- C. Huang and
**H. Jiao***, “C3MLS: a 0.12-nW Leakage and 18.11-fJ/Transition Level Shifter with Cross-Coupled and Current Mirror Hybrid Structure for Ultra-Wide Range Level Conversions,”*Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC)*, November 2022. - X. Wang^, G. Li, J. Sun, H. Fan, Y. Chen, and
**H. Jiao***, “Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks,”*Proc. of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)*, November 2022. - C. Xie^, C. Yang, and
**H. Jiao***, “A Karnaugh Map Approximate Adder With Intrinsic Error Compensation,”*Proc. of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)*, November 2022. - M. Liu^, Y. He, and
**H. Jiao***, “An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator,”*Proc. of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)*, November 2022. - C. Zhou^, M. Liu, S. Qiu, Y. He, and
**H. Jiao***, “An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance,”*Proceedings of the**IEEE/ACM Design Automation Conference (DAC)*, pp. 241-246, December 2021. - K. van Noord, W. Wang*, and
**H. Jiao**, “Insights of 3D Input CNN in EEG-based Emotion Recognition,”*Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)*, pp. 212-215, October 2021. - M. Liu^, Y. He, and
**H. Jiao***, “Efficient Zero-Activation-Skipping for On-Chip Low-Energy CNN Acceleration,”*Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)*, pp. 1-4, June 2021. - S. Lu^, L. Lu, S. Zhang, and
**H. Jiao***, “A Pull-up Adaptive Sense Amplifier Based on Dual-Gate IGZO TFTs,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May 2021. - H.-M. Lam, S. Lu, H. Qiu,
**H. Jiao**, M. Zhang, and S. Zhang*, “Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May 2021. - C. Xu^, X. Su, Z. Shen, D. Wang, Y. Tan, Z. Liu,
**H. Jiao**, J. Liu, and H. Liao, “A Hybrid Digital Transmitter Architecture for High-Efficiency and High-Speed Applications,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May 2021. - H.-M. Lam,
**H. Jiao***, M. Zhang, and S. Zhang*, “Data Line Driver with Gray-level Dependent Far-End Auxiliary Driving for Large AMOLED Display Panel,”*Wiley SID Symposium Digest of Technical Papers (SID)*, May 2021. - H.-M. Lam, H. Qiu, C. Li, J. Wen, W. Bai, J. Huang, C. Xu, X. Huo, S. Yi, W. Zeng, D. Zhang, T. Lei, S. Lu, J. An, C. Liao, M. Zhang,
**H. Jiao***, and S. Zhang*, “OLEDoS Microdisplay with OLED Threshold Voltage Detection and Fast-Progressive Compensation,”*Wiley SID Symposium Digest of Technical Papers (SID)*, May 2021. - Y. Huang^ and
**H. Jiao***, “An Ultra-Low-Voltage Single-Phase Adaptive Pulse Latch with Redundant Toggling Elimination,” P*roceedings of the IEEE International Conference on Solid-State & Integrated Circuit Technology (ICSICT)*, pp. 1-3, November 2020. **H. Jiao***and Z. Zhang, “A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May 2020.- H. Qiu, J. Liang, W. Bai, H. Lam, J. An, C. Liao, M. Zhang,
**H. Jiao**, and S. Zhang*, “A Compensation System Using Analog Voltage Adder with Continuous Output for AMOLED Display Drivers,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May 2020. - W. Bai^, S. Yi, H. Lam, M. Zhang, S. Zhang, and
**H. Jiao***, “A 1.05% Sensing Error Current Comparator for AMOLED Displays with External Compensation,”*Wiley SID Symposium Digest of Technical Papers (SID)*, pp. 1494-1497, May 2020. - P. Detterer^*, C. Erdin, J. Huisken,
**H. Jiao**, M. Nabi, T. Basten, J. Pineda de Gyvez, “Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator,”*Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE)*, pp. 1674-1679, March 2020. - K. Singh^*, B. de Bruin, J. Huisken,
**H. Jiao**, H. Corporaal, and J. Pineda de Gyvez, “Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems,”*Proceedings of the IEEE S3S Conference (S3S)*, October 2019. - K. Singh^*, B. de Bruin, J. Huisken,
**H. Jiao**, and J. Pineda de Gyvez, “Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation,”*Proceedings of the IEEE International SoC Conference (SOCC)*, pp. 370-375, September 2019. - J. Sun^ and
**H. Jiao***, “A 12T Low-Power Standard-Cell Based SRAM Circuit for Ultra-Low-Voltage Operations,”*Proceedings of the IEEE International Conference on IC Design and Technology (ICICDT)*, pp. 145-148, June 2019. - C. Yang^ and
**H. Jiao***, “Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations,”*Proceedings of the IEEE International Conference on IC Design and Technology (ICICDT)*, pp. 78-81, June 2019. - Y. Chen^ and
**H. Jiao***, “Standard Cell Optimization for Ultra-Low-Voltage Digital Circuits,”*Proceedings of the IEEE International Conference on IC Design and Technology (ICICDT)*, pp. 74-77, June 2019. - X. Huo^, W. Bai, H.-M. Lam, C. Liao, M. Zhang, S. Zhang, and
**H. Jiao***, “A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May 2019. - P. Detterer^*, C. Erdin, M. Nabi, J. Pineda de Gyvez, T. Basten, and
**H. Jiao**, “Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver,”*Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE)*, pp. 102-107, March 2019. - Y. Sun*, W. He, Z. Mao,
**H. Jiao**, and V. Kursun, “Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes,”*Proceedings of the IEEE International Conference on Electronics, Information, and Communication (ICEIC)*, pp. 1-2, January 2019. - L. Katselas^*, A. Hatzopoulos,
**H. Jiao**, C. Papameletis, and E. J. Marinissen, “Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs,”*Proceedings of the IEEE International Test Conference (ITC)*, pp. 1-9, October 2018. - P. Detterer^*, C. Erdin, M. Nabi, T. Basten, and
**H. Jiao**, “Understanding the Impact of Circuit-Level Inaccuracy on Sensor Network Performance,”*Proceedings of the ACM Symposium on Performance Evaluation of Wireless Ad Hoc, Sensor, and Ubiquitous Networks (PE-WASUN)*, pp. 107-114, October 2018. - L. Waeijen*,
**H. Jiao**, H. Corporaal, and Y. He, “Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude,”*Proceedings of the IEEE Euromicro Conference on Digital System Design (DSD)*, pp. 54-61, August 2018. - F. Hu^, M. Zhang, and
**H. Jiao***, “Achieving Low Power Classification with Classifier Ensemble,”*Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)*, pp. 16-21, July 2018. - S. Yi^, X. Huo, C. Liao, Y. Wang, J. Wu,
**H. Jiao**, M. Zhang, and S. Zhang*, “An a-IGZO TFT Pixel Circuit for AMOLED Display Systems With Compensation for Mobility and Threshold Voltage Variations,”*Proceedings of the IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)*, pp. 1-2, June 2018. - Y. Li^*, M. Shao,
**H. Jiao**, A. Cron, S. Bhatia, and E. J. Marinissen, “IEEE Std P1838’s Flexible Parallel Port and its Specification with Google’s Protocol Buffers,”*Proceedings of the IEEE European Test Symposium (ETS)*, pp. 1-6, May 2018. - K. Singh^*, O. A. Rodriguez Rosas,
**H. Jiao**, J. Huisken, and J. Pineda de Gyvez, “Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, May 2018. - H. Qiu, W. Lu, S. Zhang, and
**H. Jiao***, “A Low-power Time-Interleaving Analog Adder for Externally Compensated AMOLED/Micro-LED Displays,”*Wiley SID Symposium Digest of Technical Papers (SID)*, pp. 1399-1402, May 2018. - X. Huo^, C. Liao, J. Wu, S. Yi, Y. Wang,
**H. Jiao**, and S. Zhang*, “An OLEDoS Pixel Circuit with Extended Data Voltage Range for High Resolution Micro-Displays,”*Wiley SID Symposium Digest of Technical Papers (SID)*, pp. 1373-1376, May 2018. - K. Singh^*,
**H. Jiao**, J. Huisken, H. Fatemi, and J. Pineda de Gyvez, “Low Power Latch Based Design with Smart Retiming,”*Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED)*, pp. 329-334, March 2018. - Y. Sun*, W. He, Z. Mao,
**H. Jiao**, and V. Kursun, “Metallic-Carbon-Nanotube-Removal Tolerant SRAM Cell with 9 Transistors,”*Proceedings of the IEEE International Conference on ASIC (ASICON)*, pp. 908-911, October 2017 (Invited Paper). - L. Katselas^*, A. Athanasiadis, A. Hatzopoulos,
**H. Jiao**, C. Papameletis, and E. J. Marinissen, “Embedded Toggle Generator to Control the Switching Activity during Test of Digital 2D-SoCs and 3D-SICs,”*Proceedings of the IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)*, pp. 1-8, September 2017. - M. van Leussen^, J. Huisken, L. Wang,
**H. Jiao***, and J. Pineda de Gyvez, “Reconfigurable Support Vector Machine Classifier with Approximate Computing,”*Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)*, pp. 13-18, July 2017. - H. Ahmadi Balef^*,
**H. Jiao**, J. Pineda de Gyvez, and K. Goossens, “An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops,”*Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED)*, pp. 209-214, March 2017. **H. Jiao***, Y. Qiu, and V. Kursun, “Variations-Tolerant 9T SRAM Circuit with Robust and Low Leakage SLEEP Mode,”*Proceedings of the IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)*, pp. 39-42, July 2016.- E. J. Marinissen*, T. McLaurin, and
**H. Jiao**, “IEEE Std P1838: DfT Standard-under-Development for 2.5D-, 3D-, and 5.5D-SICs,”*Proceedings of the IEEE European Test Symposium (ETS)*, pp. 1-10, May 2016. - S. Hamdioui*, L. Xie, H. A. Du Nguyen, M. Taouil, K. Bertels, H. Corporaal,
**H. Jiao**, F. Catthoor, D. Wouters, L. Eike, and J. van Lunteren, “Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications,”*Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE)*, pp. 1718-1725, March 2015. - Y. Sun*,
**H. Jiao**, and V. Kursun, “Low-Leakage 9-CN-MOSFET SRAM Cell with Enhanced Read and Write Voltage Margins,”*Proceedings of the IEEE International Conference on Microelectronics (ICM)*, pp. 164-167, December 2014**(Best Paper Award)**. **H. Jiao***and V. Kursun, “Novel High Electrical Quality Seven-Transistor Memory Cell with Asymmetrical Ground Gating,”*Proceedings of the IEEE International SoC Design Conference (ISOCC)*, pp. 255-258, November 2013.**H. Jiao***and V. Kursun, “Characterization of Mode Transition Timing Overhead for Net Energy Savings in Low-Noise MTCMOS Circuits,”*Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC)*, pp. 150-155, October 2013.**H. Jiao***and V. Kursun, “Ground Gated 8T SRAM Cells with Enhanced Read and Hold Data Stability,”*Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)*, pp. 52-57, August 2013.- S. M. Salahuddin*,
**H. Jiao**, and V. Kursun, “Characterization of FinFET SRAM Cells with Asymmetrically Gate Underlapped Bitline Access Transistors under Process Parameter Fluctuations,”*Proceedings of the IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)*, pp. 1-2, June 2013. - S. M. Salahuddin*,
**H. Jiao**, and V. Kursun, “Low-Leakage Hybrid FinFET SRAM Cell with Asymmetrical Gate Overlap / Underlap Bitline Access Transistors for Enhanced Read Data Stability,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 2331-2334, May 2013. - S. M. Salahuddin*,
**H. Jiao**, and V. Kursun, “A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability,”*Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED)*, pp. 353-358, March 2013. **H. Jiao***and V. Kursun, “Characterization of Noise-Aware MTCMOS Circuits with Sleep Signal Slew Rate Modulation under Process Parameter Variations,”*Proceedings of the IEEE International Conference on Electronics, Information, and Communication*, January 2013.**H. Jiao***and V. Kursun, “Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits,”*Proceedings of the IEEE International SoC Design Conference (ISOCC)*, pp. 466-469, November 2012**(SoC Design Group Award)**.**H. Jiao***and V. Kursun, “Low Power and Robust Ground Gated Memory Banks with Combined Write Assist Techniques,”*Proceedings of the IEEE Faible Tension Faible Consommation (FTFC)*, June 2012.**H. Jiao***and V. Kursun, “Full-Custom Design of Low Leakage Data Preserving Ground Gated 6T SRAM Cells to Facilitate Single-Ended Write Operations,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 484-487, May 2012.**H. Jiao***and V. Kursun, “Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits,”*Proceedings of the IEEE International SoC Conference (SOCC)*, pp. 365-370, September 2011.**H. Jiao***and V. Kursun, “Asymmetrical Ground Gating for Low Leakage and Data Robust Sleep Mode in Memory Banks,”*Proceedings of the IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)*, pp. 205-208, April 2011.**H. Jiao***and V. Kursun, “Power Gated SRAM Circuits with Data Retention Capability and High Immunity to Noise: A Comparison for Reliability in Low Leakage Sleep Mode,”*Proceedings of the IEEE International SoC Design Conference (ISOCC)*, pp. 5-8, November 2010 (Invited Paper).**H. Jiao***and V. Kursun, “How Forward Body Bias Helps to Reduce Ground Bouncing Noise and Silicon Area in MTCMOS Circuits: Divulging the Basic Mechanism,”*Proceedings of the IEEE International SoC Design Conference (ISOCC)*, pp. 9-12, November 2010 (Invited Paper).**H. Jiao***and V. Kursun, “Reactivation Noise Suppression with Threshold Voltage Tuning in Sequential MTCMOS Circuits,”*Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC)*, pp. 347-351, September 2010.**H. Jiao***and V. Kursun, “High-Speed and Low-Leakage MTCMOS Memory Registers,”*Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED)*, pp. 17-22, August 2010.**H. Jiao***and V. Kursun, “Dynamic Forward Body Bias Enhanced Tri-Mode MTCMOS,”*Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED)*, pp. 33-37, August 2010.**H. Jiao***and V. Kursun, “Smooth Awakenings: Reactivation Noise Suppressed Low-Leakage and Robust MTCMOS Flip-Flops,”*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS),*pp. 3845-3848, May 2010.**H. Jiao***and V. Kursun, “Ground Bouncing Noise Aware Sequential MTCMOS Circuits with Data Retention Capability,”*Proceedings of the IEEE International Symposium on Integrated Circuits (ISIC)*, pp. 534-537, December 2009 (Invited Paper).**H. Jiao***and V. Kursun, “Sleep Transistor Forward Body Bias: An Extra Knob to Lower Ground Bouncing Noise in MTCMOS Circuits,”*Proceedings of the IEEE International SoC Design Conference (ISOCC)*, pp. 216-219, November 2009 (Invited Paper).**H. Jiao***and V. Kursun, “Ground Bouncing Noise Suppression Techniques for MTCMOS Circuits,”*Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED)*, pp. 64-70, July 2009.**H. Jiao***and L. Chen, “Cellwise OPC Based on Reduced Standard Cell Library,”*Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED),*pp. 810-814, March 2008.

# Patents

- V. Kursun, S. M. Salahuddin, and H. Jiao, “SRAM with Asymmetrical Transistors and Method for Controlling the Same,” Chinese Patent, CN201310076418.6, January 20, 2016.
- V. Kursun, H. Zhu, and H. Jiao, “Static Random Access Memory and Method for Controlling the Same,” Chinese Patent, CN201110359652.0, December 3, 2014.