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Book Chapters

  1. H. Jiao and V. Kursun, “Tri-Mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits,” VLSI-SoC: Forward-Looking Trends in IC and System Design, J. L. Ayala, D. A. Atienza, and R. Reis, (Eds.), Springer, pp. 258 – 290, 2012, ISBN 978-3-642-28565-3.

Journal Papers

* Corresponding author     ^ Supervised student as first author

  1. H.-M. Lam, F. Guo, H. Qiu, M. Zhang, H. Jiao*, and S. Zhang, “Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers,” IEEE Transactions on Circuits and Systems for Video Technology, 2020.
  2. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density,” IEEE Transactions on Circuits and Systems I, 2020.
  3. J. Liang, S. Yi, W. Bai, L. Wang, C. Zhan, C. Liao, H.-M. Lam, M. Zhang, S. Zhang, H. Jiao*, “A 80 dB PSRR 4.99 ppm/°C TC Bandgap Reference with Nonlinear Compensation,” Elsevier Microelectronics Journal, Vol. 95, 2020.
  4. X. Huo^, C. Liao, M. Zhang, H. Jiao*, and S. Zhang, “A Pixel Circuit With Wide Data Voltage Range for OLEDoS Microdisplays With High Uniformity,” IEEE Transactions on Electron Devices, Vol. 66, No. 11, pp. 4798-4804, November 2019.
  5. H.-M. Lam, Y. Wang, M. Zhang, H. Jiao*, and S. Zhang, “A Compact Pixel Circuit for Externally Compensated AMOLED Displays,” IEEE Journal of the Electron Devices Society, Vol. 6, pp. 936-941, December 2018.
  6. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded Memory,” IEEE Transactions on Electron Devices, Vol. 65, No. 3, pp. 1230-1238, March 2018.
  7. H. Jiao, R. Wang, and Y. He, “Crosstalk-Noise-Aware Bus Coding with Low-Power Ground-Gated Repeaters,” Wiley International Journal of Circuit Theory and Applications, Vol. 46, No. 2, pp. 280-289, February 2018.
  8. Y. Sun, W. He, Z. Mao, H. Jiao*, and V. Kursun, “High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes,” IEEE Transactions on Device and Materials Reliability, Vol. 17, No. 1, pp. 20-31, March 2017.
  9. H. Jiao, Y. Qiu, and V. Kursun, “Variability-Aware 7T SRAM Circuit with Low Leakage High Data Stability SLEEP Mode,” Elsevier Integration, the VLSI Journal, Vol. 53, pp. 68-79, March 2016.
  10. H. Jiao, Y. Qiu, and V. Kursun, “Low Power and Robust Memory Circuits with Asymmetrical Ground Gating,” Elsevier Microelectronics Journal, Vol. 48, pp. 109-119, February 2016.
  11. S. M. Salahuddin, H. Jiao, and V. Kursun, “FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability,” Transactions on Electrical and Electronic Materials, Vol. 16, No. 6, pp. 293-302, December 2015.
  12. Y. Sun, H. Jiao, and V. Kursun, “A Novel Robust and Low-Leakage SRAM Cell with Nine Carbon Nanotube Transistors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1729-1739, September 2015.
  13. H. Jiao and V. Kursun, “Mode Transition Timing and Energy Overhead Analysis in Noise-Aware MTCMOS Circuits,” Elsevier Microelectronics Journal, Vol. 45, No. 8, pp. 1125-1131, August 2014.
  14. H. Jiao and V. Kursun, “Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, pp. 533-545, March 2013.
  15. H. Jiao and V. Kursun, “Threshold Voltage Tuning for Faster Activation with Lower Noise in Tri-Mode MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, pp. 741-745, April 2012.
  16. H. Jiao and V. Kursun, “Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, pp. 763-773, May 2011.
  17. H. Jiao and V. Kursun, “Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias,” World Scientific Journal of Circuits, Systems, and Computers (Special Issue on Green Integrated Circuits and Systems, Invited Paper), Vol. 20, No. 1, pp. 125-145, February 2011.
  18. H. Jiao and V. Kursun, “Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 57, No. 8, pp. 2053-2065, August 2010.
  19. H. Jiao and V. Kursun, “Low-Leakage and Compact Registers with Easy-Sleep Mode,” ASP Journal of Low Power Electronics, Vol. 6, No. 2, pp. 263-279, August 2010.
  20. H. Jiao, L. Chen, Z. Li, Q. Yang, and T. Ye, “OPC Reuse Based on A Reduced Standard Cell Library,” IOPscience Journal of Semiconductors, Vol. 29, No. 5, pp. 1016-1021, May 2008.

Conference Papers

* Corresponding author     ^ Supervised student as first author

  1. H. Jiao and Z. Zhang, “A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.
  2. H. Qiu, J. Liang, W. Bai, H. Lam, J. An, C. Liao, M. Zhang, H. Jiao, and S. Zhang, “A Compensation System Using Analog Voltage Adder with Continuous Output for AMOLED Display Drivers,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.
  3. W. Bai^, S. Yi, H. Lam, M. Zhang, S. Zhang, and H. Jiao*, “A 1.05% Sensing Error Current Comparator for AMOLED Displays with External Compensation,” Wiley SID Symposium Digest of Technical Papers, May 2020.
  4. P. Detterer^, C. Erdin, J. Huisken, H. Jiao, M. Nabi, T. Basten, J. Pineda de Gyvez, “Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator,” Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 2020.
  5. K. Singh^, B. de Bruin, J. Huisken, H. Jiao, H. Corporaal, and J. Pineda de Gyvez, “Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems,” Proceedings of the IEEE S3S Conference (S3S), October 2019.
  6. K. Singh^, B. de Bruin, J. Huisken, H. Jiao, and J. Pineda de Gyvez, “Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation,” Proceedings of the IEEE International SoC Conference (SOCC), pp. 370-375, September 2019.
  7. J. Sun^ and H. Jiao*, “A 12T Low-Power Standard-Cell Based SRAM Circuit for Ultra-Low-Voltage Operations,” Proceedings of the IEEE International Conference on IC Design and Technology (ICICDT), pp. 145-148, June 2019.
  8. C. Yang^ and H. Jiao*, “Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations,” Proceedings of the IEEE International Conference on IC Design and Technology (ICICDT), pp. 78-81, June 2019.
  9. Y. Chen^ and H. Jiao*, “Standard Cell Optimization for Ultra-Low-Voltage Digital Circuits,” Proceedings of the IEEE International Conference on IC Design and Technology (ICICDT), pp. 74-77, June 2019.
  10. X. Huo^, W. Bai, H.-M. Lam, C. Liao, M. Zhang, S. Zhang, and H. Jiao*, “A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2019.
  11. P. Detterer^, C. Erdin, M. Nabi, J. Pineda de Gyvez, T. Basten, and H. Jiao*, “Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver,” Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 102-107, March 2019.
  12. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes,” Proceedings of the IEEE International Conference on Electronics, Information, and Communication (ICEIC), pp. 1-2, January 2019.
  13. L. Katselas^, A. Hatzopoulos, H. Jiao, C. Papameletis, and E. J. Marinissen, “Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs,” Proceedings of the IEEE International Test Conference (ITC), pp. 1-9, October 2018.
  14. P. Detterer^, C. Erdin, M. Nabi, T. Basten, and H. Jiao, “Understanding the Impact of Circuit-Level Inaccuracy on Sensor Network Performance,” Proceedings of the ACM Symposium on Performance Evaluation of Wireless Ad Hoc, Sensor, and Ubiquitous Networks (PE-WASUN), pp. 107-114, October 2018.
  15. L. Waeijen, H. Jiao, H. Corporaal, and Y. He, “Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude,” Proceedings of the IEEE Euromicro Conference on Digital System Design (DSD), pp. 54-61, August 2018.
  16. F. Hu^, M. Zhang, and H. Jiao*, “Achieving Low Power Classification with Classifier Ensemble,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 16-21, July 2018.
  17. S. Yi^, X. Huo, C. Liao, Y. Wang, J. Wu, H. Jiao, M. Zhang, and S. Zhang, “An a-IGZO TFT Pixel Circuit for AMOLED Display Systems With Compensation for Mobility and Threshold Voltage Variations,” Proceedings of the IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 1-2, June 2018.
  18. Y. Li^, M. Shao, H. Jiao, A. Cron, S. Bhatia, and E. J. Marinissen, “IEEE Std P1838’s Flexible Parallel Port and its Specification with Google’s Protocol Buffers,” Proceedings of the IEEE European Test Symposium (ETS), pp. 1-6, May 2018.
  19. K. Singh^, O. A. Rodriguez Rosas, H. Jiao, J. Huisken, and J. Pineda de Gyvez, “Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
  20. H. Qiu, W. Lu, S. Zhang, and H. Jiao*, “A Low-power Time-Interleaving Analog Adder for Externally Compensated AMOLED/Micro-LED Displays,” Wiley SID Symposium Digest of Technical Papers, pp. 1399-1402, May 2018.
  21. X. Huo^, C. Liao, J. Wu, S. Yi, Y. Wang, H. Jiao, and S. Zhang, “An OLEDoS Pixel Circuit with Extended Data Voltage Range for High Resolution Micro-Displays,” Wiley SID Symposium Digest of Technical Papers, pp. 1373-1376, May 2018.
  22. K. Singh^, H. Jiao, J. Huisken, H. Fatemi, and J. Pineda de Gyvez, “Low Power Latch Based Design with Smart Retiming,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 329-334, March 2018.
  23. Y. Sun, W. He, Z. Mao, H. Jiao, and V. Kursun, “Metallic-Carbon-Nanotube-Removal Tolerant SRAM Cell with 9 Transistors,” Proceedings of the IEEE International Conference on ASIC (ASICON), pp. 908-911, October 2017 (Invited Paper).
  24. L. Katselas^, A. Athanasiadis, A. Hatzopoulos, H. Jiao, C. Papameletis, and E. J. Marinissen, “Embedded Toggle Generator to Control the Switching Activity during Test of Digital 2D-SoCs and 3D-SICs,” Proceedings of the IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 1-8, September 2017.
  25. M. van Leussen^, J. Huisken, L. Wang, H. Jiao*, and J. Pineda de Gyvez, “Reconfigurable Support Vector Machine Classifier with Approximate Computing,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 13-18, July 2017.
  26. H. Ahmadi Balef^, H. Jiao, J. Pineda de Gyvez, and K. Goossens, “An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 209-214, March 2017.
  27. H. Jiao, Y. Qiu, and V. Kursun, “Variations-Tolerant 9T SRAM Circuit with Robust and Low Leakage SLEEP Mode,” Proceedings of the IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 39-42, July 2016.
  28. E. J. Marinissen, T. McLaurin, and H. Jiao, “IEEE Std P1838: DfT Standard-under-Development for 2.5D-, 3D-, and 5.5D-SICs,” Proceedings of the IEEE European Test Symposium (ETS), pp. 1-10, May 2016.
  29. S. Hamdioui, L. Xie, H. A. Du Nguyen, M. Taouil, K. Bertels, H. Corporaal, H. Jiao, F. Catthoor, D. Wouters, L. Eike, and J. van Lunteren, “Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications,” Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 1718-1725, March 2015.
  30. Y. Sun, H. Jiao, and V. Kursun, “Low-Leakage 9-CN-MOSFET SRAM Cell with Enhanced Read and Write Voltage Margins,” Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014 (Best Paper Award).
  31. H. Jiao and V. Kursun, “Novel High Electrical Quality Seven-Transistor Memory Cell with Asymmetrical Ground Gating,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 255-258, November 2013.
  32. H. Jiao and V. Kursun, “Characterization of Mode Transition Timing Overhead for Net Energy Savings in Low-Noise MTCMOS Circuits,” Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 150-155, October 2013.
  33. H. Jiao and V. Kursun, “Ground Gated 8T SRAM Cells with Enhanced Read and Hold Data Stability,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 52-57, August 2013.
  34. S. M. Salahuddin, H. Jiao, and V. Kursun, “Characterization of FinFET SRAM Cells with Asymmetrically Gate Underlapped Bitline Access Transistors under Process Parameter Fluctuations,” Proceedings of the IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 1-2, June 2013.
  35. S. M. Salahuddin, H. Jiao, and V. Kursun, “Low-Leakage Hybrid FinFET SRAM Cell with Asymmetrical Gate Overlap / Underlap Bitline Access Transistors for Enhanced Read Data Stability,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2331-2334, May 2013.
  36. S. M. Salahuddin, H. Jiao, and V. Kursun, “A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 353-358, March 2013.
  37. H. Jiao and V. Kursun, “Characterization of Noise-Aware MTCMOS Circuits with Sleep Signal Slew Rate Modulation under Process Parameter Variations,” Proceedings of the IEEE International Conference on Electronics, Information, and Communication, January 2013.
  38. H. Jiao and V. Kursun, “Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 466-469, November 2012 (SoC Design Group Award).
  39. H. Jiao and V. Kursun, “Low Power and Robust Ground Gated Memory Banks with Combined Write Assist Techniques,” Proceedings of the IEEE Faible Tension Faible Consommation (FTFC), June 2012.
  40. H. Jiao and V. Kursun, “Full-Custom Design of Low Leakage Data Preserving Ground Gated 6T SRAM Cells to Facilitate Single-Ended Write Operations,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 484-487, May 2012.
  41. H. Jiao and V. Kursun, “Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits,” Proceedings of the IEEE International SoC Conference (SOCC), pp. 365-370, September 2011.
  42. H. Jiao and V. Kursun, “Asymmetrical Ground Gating for Low Leakage and Data Robust Sleep Mode in Memory Banks,” Proceedings of the IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 205-208, April 2011.
  43. H. Jiao and V. Kursun, “Power Gated SRAM Circuits with Data Retention Capability and High Immunity to Noise: A Comparison for Reliability in Low Leakage Sleep Mode,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 5-8, November 2010 (Invited Paper).
  44. H. Jiao and V. Kursun, “How Forward Body Bias Helps to Reduce Ground Bouncing Noise and Silicon Area in MTCMOS Circuits: Divulging the Basic Mechanism,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 9-12, November 2010 (Invited Paper).
  45. H. Jiao and V. Kursun, “Reactivation Noise Suppression with Threshold Voltage Tuning in Sequential MTCMOS Circuits,” Proceedings of the IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 347-351, September 2010.
  46. H. Jiao and V. Kursun, “High-Speed and Low-Leakage MTCMOS Memory Registers,” Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED), pp. 17-22, August 2010.
  47. H. Jiao and V. Kursun, “Dynamic Forward Body Bias Enhanced Tri-Mode MTCMOS,” Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED), pp. 33-37, August 2010.
  48. H. Jiao and V. Kursun, “Smooth Awakenings: Reactivation Noise Suppressed Low-Leakage and Robust MTCMOS Flip-Flops,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3845-3848, May 2010.
  49. H. Jiao and V. Kursun, “Ground Bouncing Noise Aware Sequential MTCMOS Circuits with Data Retention Capability,” Proceedings of the IEEE International Symposium on Integrated Circuits (ISIC), pp. 534-537, December 2009 (Invited Paper).
  50. H. Jiao and V. Kursun, “Sleep Transistor Forward Body Bias: An Extra Knob to Lower Ground Bouncing Noise in MTCMOS Circuits,” Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 216-219, November 2009 (Invited Paper).
  51. H. Jiao and V. Kursun, “Ground Bouncing Noise Suppression Techniques for MTCMOS Circuits,” Proceedings of the IEEE/ACM Asia Symposium on Quality Electronic Design (ASQED), pp. 64-70, July 2009.
  52. H. Jiao and L. Chen, “Cellwise OPC Based on Reduced Standard Cell Library,” Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 810-814, March 2008.

Patents

  1. V. Kursun, S. M. Salahuddin, and H. Jiao, “SRAM with Asymmetrical Transistors and Method for Controlling the Same,” Chinese Patent, CN201310076418.6, January 20, 2016.
  2. V. Kursun, H. Zhu, and H. Jiao, “Static Random Access Memory and Method for Controlling the Same,” Chinese Patent, CN201110359652.0, December 3, 2014.

Thesis

  • Doctoral Thesis
    Noise Mitigation in Low Leakage MTCMOS Circuits
    Supervisor: Prof. Volkan Kursun
    The Hong Kong University of Science and Technology, Hong Kong
  • Master Thesis
    Research on OPC Reuse Based on Reduced Standard Cell Library
    Supervisor: Prof. Tianchun Ye and Prof. Lan Chen
    Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
  • Bachelor Thesis
    Mixed-signal Circuit System Based on CPLD and MCU
    Supervisor: Prof. Wei Jiang
    Shandong University, Shandong, China